A variety of thin-film piezoelectric resonators using thickness vibration modes of piezoelectric thin films have been proposed.
For example, a thin-film piezoelectric resonator 1 as shown in FIG. 1 has a SiO2 layer 3 on a substrate 2, and a thin-film portion 4 on the SiO2 layer 3. The thin-film portion includes a piezoelectric thin film 4c sandwiched between opposing electrodes 4a and 4b. An opening 5 is formed in the substrate 2 so that the piezoelectric thin film 4c between the opposing electrodes 4a and 4b and the underlying SiO2 layer 3 produce thickness longitudinal vibration in a second harmonic mode, as indicated by, for example, dotted lines 6. When the SiO2 layer 3 has a thickness of ts and the piezoelectric thin film has a thickness of tp, the thickness ratio tp/ts is set so that the antinode of the thickness vibration is substantially located on the lower electrode 4a. Thus, the electromechanical coupling coefficient of the thin-film piezoelectric resonator 1 can be maximized. The thickness ratio tp/ts is a value other than 1 because the SiO2 layer has a different acoustic velocity from the piezoelectric thin film 4c (see, for example, Patent Document 1).
It has been proposed that higher-order anharmonic spuriouses are reduced in the thin-film piezoelectric resonator using thickness longitudinal vibration by providing an irregular nonrectangular polygonal overlap between the upper and lower electrodes (see, for example, Patent document 2).    Patent Document 1: Japanese Unexamined Patent Application Publication No. 2003-87085 (pp. 3-4, FIG. 1)    Patent Document 2: Japanese Unexamined Patent Application Publication No. 2000-332568 (p. 4, FIG. 4)
However, in order to vibrate the nonrectangular overlap between the upper and lower electrodes without any problem, the device chip must have a rectangular area at least circumscribing the nonrectangular shape. The rectangular area must be larger than that in the example having a rectangular overlap between the upper and lower electrodes, and it is difficult to downsize the device chip.